How to Setup the Readout Trigger

The DAQ system is triggered via JLab Trigger Interface (TI). The TI can take up to 4 trigger type inputs. Each type can be a combination of various detector triggers. For example, if you have 3 HPGe detectors and you want to read any one of them if it has a valid signal, the trigger circuit would be similar to the Figure B.1. After all the detector signals are discriminated, an OR of all the discriminated signals is done. This is defined as (TRIG OR). The output of TRIG OR is taken to a gate fan in/out module. An output from the gate fan is taken as a scaler input and the other output is used to generate a vetoed trigger. The veto consists of an overlap between the VME Busy (Obtained by the Busy output of the TI), and the Delayed Trigger. The Delayed trigger is implemented to account for the conversion time of the CAMAC modules. For example, the conversion time of L2249W QDC is 110 $\mu$sec. Therefore, the gate width of the gate-delay generator should be set to atleast 110 $\mu$sec. The outputs from the Vetoed trigger (TRIG VETO) are then used to trigger the VME module (TI), and generate the ADC gates. A copy of the TRIG VETO is used as a scaler input. The ratio of the vetoed triggers to the total triggers is the live time of the system ( LT = (TRIG VETO)/(TRIG OR)).

Figure B.1: The Trigger Circuit.

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A common problem with having a large dead time is double- (or multi-) pulsing. If the discrinated outputs from the detectors are multi-pulsing, you will measure a large incorrect dead time. The maximum rate the DAQ should be able to handle, to the first order, is given by the 1/(BUSY OR). For instance, if the busy overlap has a total time of 120 $\mu$sec, the maximum rate the DAQ can take without going 100 % dead time would be $\sim$8.3 kHz.